The semiconductor industry has experienced rapid growth and demands for highly integrated semiconductor devices are increasing. Technological advances in integrated circuit (IC) design and materials have produced generations of ICs. Each generation has smaller and more complex circuits than previous generations. In the course of IC evolution, functional density has generally increased while geometric size (i.e., the smallest component (or line) that can be created through a fabrication process) has decreased.
As the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design issues have resulted in the development of three-dimensional designs, such as the fin field effect transistor (FinFET). FinFETs are fabricated with a thin vertical “fin” (or fin structure) extending from a substrate. The channel of the FinFET is formed in this vertical fin. A gate is provided over three sides (e.g., wrapping) the fin. Advantages of the FinFET may include reducing the short channel effect and increasing the current flow.
Although existing FinFETs and methods of fabricating FinFETs have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects. For example, as the size of the FinFET has been reduced, is has become a challenge to integrate a fin-trim process into the fabrication processes of the FinFET device.